Struct L2And3CacheTlbInfo Copy item path

impl L2And3CacheTlbInfo

pub fn dtlb_2m_4m_associativity(&self) -> Associativity

L2 Data TLB associativity for 2-MB and 4-MB pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn dtlb_2m_4m_size(&self) -> u16

L2 Data TLB number of entries for 2-MB and 4-MB pages.

The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn itlb_2m_4m_associativity(&self) -> Associativity

L2 Instruction TLB associativity for 2-MB and 4-MB pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn itlb_2m_4m_size(&self) -> u16

L2 Instruction TLB number of entries for 2-MB and 4-MB pages.

The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn dtlb_4k_associativity(&self) -> Associativity

L2 Data TLB associativity for 4K pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn dtlb_4k_size(&self) -> u16

L2 Data TLB number of entries for 4K pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn itlb_4k_associativity(&self) -> Associativity

L2 Instruction TLB associativity for 4K pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn itlb_4k_size(&self) -> u16

L2 Instruction TLB number of entries for 4K pages.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn l2cache_line_size(&self) -> u8

L2 Cache Line size in bytes

§Platforms

✅ AMD ✅ Intel

pub fn l2cache_lines_per_tag(&self) -> u8

L2 cache lines per tag.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn l2cache_associativity(&self) -> Associativity

L2 Associativity field

§Availability

✅ AMD ✅ Intel

pub fn l2cache_size(&self) -> u16

Cache size in KB.

§Platforms

✅ AMD ✅ Intel

pub fn l3cache_line_size(&self) -> u8

L2 Cache Line size in bytes

§Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn l3cache_lines_per_tag(&self) -> u8

L2 cache lines per tag.

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn l3cache_associativity(&self) -> Associativity

L2 Associativity field

§Availability

✅ AMD ❌ Intel (reserved=0)

pub fn l3cache_size(&self) -> u16

Specifies the L3 cache size range

(L3Size[31:18] * 512KB) <= L3 cache size < ((L3Size[31:18]+1) * 512KB).

§Platforms

✅ AMD ❌ Intel (reserved=0)

Trait Implementations§

impl Debug for L2And3CacheTlbInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more

impl PartialEq for L2And3CacheTlbInfo

fn eq(&self, other: &L2And3CacheTlbInfo) -> bool

Tests for self and other values to be equal, and is used by ==.

1.0.0§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for L2And3CacheTlbInfo

impl StructuralPartialEq for L2And3CacheTlbInfo

Auto Trait Implementations§

impl UnwindSafe for L2And3CacheTlbInfo

Blanket Implementations§

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