ostd::arch::kernel

Struct IrqChip

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pub struct IrqChip { /* private fields */ }
Expand description

An IRQ chip.

This abstracts the hardware IRQ chips (or IRQ controllers), allowing the bus or device drivers to enable IrqLines (via, e.g., map_gsi_pin_to) regardless of the specifics of the IRQ chip.

In the x86 architecture, the underlying hardware is typically either 8259 Programmable Interrupt Controller (PIC) or I/O Advanced Programmable Interrupt Controller (I/O APIC).

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impl IrqChip

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pub fn map_gsi_pin_to( &'static self, irq_line: IrqLine, gsi_index: u32, ) -> Result<MappedIrqLine>

Maps an IRQ pin specified by a GSI number to an IRQ line.

ACPI represents all interrupts as “flat” values known as global system interrupts (GSIs). So GSI numbers are well defined on all systems where the ACPI support is present.

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pub fn map_isa_pin_to( &'static self, irq_line: IrqLine, isa_index: u8, ) -> Result<MappedIrqLine>

Maps an IRQ pin specified by an ISA interrupt number to an IRQ line.

Industry Standard Architecture (ISA) is the 16-bit internal bus of IBM PC/AT. For compatibility reasons, legacy devices such as keyboards connected via the i8042 PS/2 controller still use it.

This method is x86-specific.

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pub fn count_io_apics(&self) -> usize

Counts the number of I/O APICs.

If I/O APICs are in use, this method counts how many I/O APICs are in use, otherwise, this method return zero.

This method exists due to a workaround used in virtio-mmio bus probing. It should be removed once the workaround is retired. Therefore, only use this method if absolutely necessary.

This method is x86-specific.

Auto Trait Implementations§

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impl !Freeze for IrqChip

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impl !RefUnwindSafe for IrqChip

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impl Send for IrqChip

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impl Sync for IrqChip

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impl Unpin for IrqChip

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impl UnwindSafe for IrqChip

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