ostd/arch/x86/
mod.rs

1// SPDX-License-Identifier: MPL-2.0
2//! Platform-specific code for the x86 platform.
3/*pub mod boot;
4pub(crate) mod cpu;
5pub mod device;
6pub(crate) mod ex_table;
7pub(crate) mod io;
8pub(crate) mod iommu;
9pub(crate) mod irq;
10pub(crate) mod kernel;*/
11pub(crate) mod mm;
12/*pub(crate) mod pci;
13pub mod qemu;
14pub(crate) mod serial;
15pub(crate) mod task;
16pub mod timer;
17pub mod trap;*/
18
19/*use io::construct_io_mem_allocator_builder;
20use spin::Once;
21use x86::cpuid::{CpuId, FeatureInfo};
22
23#[cfg(feature = "cvm_guest")]
24pub(crate) mod tdx_guest;
25
26use core::sync::atomic::Ordering;
27
28use log::warn;
29
30#[cfg(feature = "cvm_guest")]
31pub(crate) fn init_cvm_guest() {
32    match ::tdx_guest::init_tdx() {
33        Ok(td_info) => {
34            crate::early_println!(
35                "[kernel] Intel TDX initialized\n[kernel] td gpaw: {}, td attributes: {:?}",
36                td_info.gpaw,
37                td_info.attributes
38            );
39        }
40        Err(::tdx_guest::tdcall::InitError::TdxGetVpInfoError(td_call_error)) => {
41            panic!(
42                "[kernel] Intel TDX not initialized, Failed to get TD info: {:?}",
43                td_call_error
44            );
45        }
46        // The machine has no TDX support.
47        Err(_) => {}
48    }
49}
50
51static CPU_FEATURES: Once<FeatureInfo> = Once::new();
52
53/// Architecture-specific initialization on the bootstrapping processor.
54///
55/// It should be called when the heap and frame allocators are available.
56///
57/// # Safety
58///
59/// This function must be called only once in the boot context of the
60/// bootstrapping processor.
61pub(crate) unsafe fn late_init_on_bsp() {
62    // SAFETY: This function is only called once on BSP.
63    unsafe { trap::init() };
64
65    let io_mem_builder = construct_io_mem_allocator_builder();
66
67    kernel::apic::init(&io_mem_builder).expect("APIC doesn't exist");
68    kernel::irq::init(&io_mem_builder);
69
70    kernel::tsc::init_tsc_freq();
71    timer::init_bsp();
72
73    // SAFETY: We're on the BSP and we're ready to boot all APs.
74    unsafe { crate::boot::smp::boot_all_aps() };
75
76    if_tdx_enabled!({
77    } else {
78        match iommu::init(&io_mem_builder) {
79            Ok(_) => {}
80            Err(err) => warn!("IOMMU initialization error:{:?}", err),
81        }
82    });
83
84    // SAFETY:
85    // 1. All the system device memory have been removed from the builder.
86    // 2. All the port I/O regions belonging to the system device are defined using the macros.
87    // 3. `MAX_IO_PORT` defined in `crate::arch::io` is the maximum value specified by x86-64.
88    unsafe { crate::io::init(io_mem_builder) };
89}
90
91/// Architecture-specific initialization on the application processor.
92///
93/// # Safety
94///
95/// This function must be called only once on each application processor.
96/// And it should be called after the BSP's call to [`init_on_bsp`].
97///
98/// [`init_on_bsp`]: crate::cpu::init_on_bsp
99pub(crate) unsafe fn init_on_ap() {
100    timer::init_ap();
101}
102
103pub(crate) fn interrupts_ack(irq_number: usize) {
104    if !cpu::context::CpuException::is_cpu_exception(irq_number) {
105        // TODO: We're in the interrupt context, so `disable_preempt()` is not
106        // really necessary here.
107        kernel::apic::get_or_init(&crate::task::disable_preempt() as _).eoi();
108    }
109}
110
111/// Returns the frequency of TSC. The unit is Hz.
112pub fn tsc_freq() -> u64 {
113    kernel::tsc::TSC_FREQ.load(Ordering::Acquire)
114}
115
116/// Reads the current value of the processor’s time-stamp counter (TSC).
117pub fn read_tsc() -> u64 {
118    use core::arch::x86_64::_rdtsc;
119
120    // SAFETY: It is safe to read a time-related counter.
121    unsafe { _rdtsc() }
122}
123
124/// Reads a hardware generated 64-bit random value.
125///
126/// Returns None if no random value was generated.
127pub fn read_random() -> Option<u64> {
128    use core::arch::x86_64::_rdrand64_step;
129
130    // Recommendation from "Intel® Digital Random Number Generator (DRNG) Software
131    // Implementation Guide" - Section 5.2.1 and "Intel® 64 and IA-32 Architectures
132    // Software Developer’s Manual" - Volume 1 - Section 7.3.17.1.
133    const RETRY_LIMIT: usize = 10;
134
135    for _ in 0..RETRY_LIMIT {
136        let mut val = 0;
137        let generated = unsafe { _rdrand64_step(&mut val) };
138        if generated == 1 {
139            return Some(val);
140        }
141    }
142    None
143}
144
145fn has_avx() -> bool {
146    use core::arch::x86_64::{__cpuid, __cpuid_count};
147
148    let cpuid_result = unsafe { __cpuid(0) };
149    if cpuid_result.eax < 1 {
150        // CPUID function 1 is not supported
151        return false;
152    }
153
154    let cpuid_result = unsafe { __cpuid_count(1, 0) };
155    // Check for AVX (bit 28 of ecx)
156    cpuid_result.ecx & (1 << 28) != 0
157}
158
159fn has_avx512() -> bool {
160    use core::arch::x86_64::{__cpuid, __cpuid_count};
161
162    let cpuid_result = unsafe { __cpuid(0) };
163    if cpuid_result.eax < 7 {
164        // CPUID function 7 is not supported
165        return false;
166    }
167
168    let cpuid_result = unsafe { __cpuid_count(7, 0) };
169    // Check for AVX-512 Foundation (bit 16 of ebx)
170    cpuid_result.ebx & (1 << 16) != 0
171}
172
173pub(crate) fn enable_cpu_features() {
174    use x86_64::registers::{control::Cr4Flags, model_specific::EferFlags, xcontrol::XCr0Flags};
175
176    CPU_FEATURES.call_once(|| {
177        let cpuid = CpuId::new();
178        cpuid.get_feature_info().unwrap()
179    });
180
181    let mut cr4 = x86_64::registers::control::Cr4::read();
182    cr4 |= Cr4Flags::FSGSBASE
183        | Cr4Flags::OSXSAVE
184        | Cr4Flags::OSFXSR
185        | Cr4Flags::OSXMMEXCPT_ENABLE
186        | Cr4Flags::PAGE_GLOBAL;
187    unsafe {
188        x86_64::registers::control::Cr4::write(cr4);
189    }
190
191    let mut xcr0 = x86_64::registers::xcontrol::XCr0::read();
192
193    xcr0 |= XCr0Flags::SSE;
194
195    if has_avx() {
196        xcr0 |= XCr0Flags::AVX;
197    }
198
199    if has_avx512() {
200        xcr0 |= XCr0Flags::OPMASK | XCr0Flags::ZMM_HI256 | XCr0Flags::HI16_ZMM;
201    }
202
203    unsafe {
204        x86_64::registers::xcontrol::XCr0::write(xcr0);
205    }
206
207    cpu::context::enable_essential_features();
208
209    unsafe {
210        // enable non-executable page protection
211        x86_64::registers::model_specific::Efer::update(|efer| {
212            *efer |= EferFlags::NO_EXECUTE_ENABLE;
213        });
214    }
215}
216
217/// Inserts a TDX-specific code block.
218///
219/// This macro conditionally executes a TDX-specific code block based on the following conditions:
220/// (1) The `cvm_guest` feature is enabled at compile time.
221/// (2) The TDX feature is detected at runtime via `::tdx_guest::tdx_is_enabled()`.
222///
223/// If both conditions are met, the `if_block` is executed. If an `else_block` is provided, it will be executed
224/// when either the `cvm_guest` feature is not enabled or the TDX feature is not detected at runtime.
225#[macro_export]
226macro_rules! if_tdx_enabled {
227    // Match when there is an else block
228    ($if_block:block else $else_block:block) => {{
229        #[cfg(feature = "cvm_guest")]
230        {
231            if ::tdx_guest::tdx_is_enabled() {
232                $if_block
233            } else {
234                $else_block
235            }
236        }
237        #[cfg(not(feature = "cvm_guest"))]
238        {
239            $else_block
240        }
241    }};
242    // Match when there is no else block
243    ($if_block:block) => {{
244        #[cfg(feature = "cvm_guest")]
245        {
246            if ::tdx_guest::tdx_is_enabled() {
247                $if_block
248            }
249        }
250    }};
251}
252
253pub use if_tdx_enabled;
254*/
ostd/arch/x86/mod.rs

ostd/arch/x86/
mod.rs
