ostd/arch/x86/vm/
types.rs

1// SPDX-License-Identifier: MPL-2.0
2
3//! Types that represent guest-visible x86 CPU state.
4
5/// Guest general-purpose registers, instruction pointer, and flags.
6#[repr(C)]
7#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
8pub struct VcpuRegs {
9    /// The `RAX` register.
10    pub rax: usize,
11    /// The `RBX` register.
12    pub rbx: usize,
13    /// The `RCX` register.
14    pub rcx: usize,
15    /// The `RDX` register.
16    pub rdx: usize,
17    /// The `RSI` register.
18    pub rsi: usize,
19    /// The `RDI` register.
20    pub rdi: usize,
21    /// The `RBP` register.
22    pub rbp: usize,
23    /// The stack pointer.
24    pub rsp: usize,
25    /// The `R8` register.
26    pub r8: usize,
27    /// The `R9` register.
28    pub r9: usize,
29    /// The `R10` register.
30    pub r10: usize,
31    /// The `R11` register.
32    pub r11: usize,
33    /// The `R12` register.
34    pub r12: usize,
35    /// The `R13` register.
36    pub r13: usize,
37    /// The `R14` register.
38    pub r14: usize,
39    /// The `R15` register.
40    pub r15: usize,
41    /// The instruction pointer.
42    pub rip: usize,
43    /// The flags register.
44    pub rflags: usize,
45}
46
47/// Guest special-register state.
48#[repr(C)]
49#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
50pub struct VcpuSregs {
51    /// The code segment.
52    pub cs: VcpuSegment,
53    /// The data segment.
54    pub ds: VcpuSegment,
55    /// The extra data segment.
56    pub es: VcpuSegment,
57    /// The `FS` segment, including the `IA32_FS_BASE` MSR value.
58    pub fs: VcpuSegment,
59    /// The `GS` segment, including the `IA32_GS_BASE` MSR value.
60    pub gs: VcpuSegment,
61    /// The stack segment.
62    pub ss: VcpuSegment,
63    /// The task register and its cached segment descriptor.
64    pub tr: VcpuSegment,
65    /// The local descriptor-table register and its cached segment descriptor.
66    pub ldt: VcpuSegment,
67    /// The global descriptor-table register.
68    pub gdt: VcpuDescTable,
69    /// The interrupt descriptor-table register.
70    pub idt: VcpuDescTable,
71    /// The `CR0` control register.
72    pub cr0: u64,
73    /// The page-fault linear address.
74    pub cr2: u64,
75    /// The page-table root and control bits.
76    pub cr3: u64,
77    /// The `CR4` control register.
78    pub cr4: u64,
79    /// The extended feature enable register.
80    pub efer: u64,
81    /// The local APIC base address and control bits.
82    pub apic_base: u64,
83    /// The pending interrupt vectors, with one bit per vector.
84    pub interrupt_bitmap: [u64; 4],
85}
86
87/// Guest segment-register state.
88///
89/// Refer to: Intel SDM Vol. 3A, 3.4.5 "Segment Descriptors".
90#[repr(C)]
91#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
92pub struct VcpuSegment {
93    /// The segment base address.
94    pub base: u64,
95    /// The effective segment limit in bytes, with granularity already applied.
96    pub limit: u32,
97    /// The segment selector.
98    pub selector: u16,
99    /// The four-bit segment type.
100    pub type_: u8,
101    /// The segment-present bit.
102    pub present: u8,
103    /// The descriptor privilege level.
104    pub dpl: u8,
105    /// The default operation size or upper-bound bit.
106    pub db: u8,
107    /// The descriptor class bit: zero for system, one for code or data.
108    pub s: u8,
109    /// The 64-bit code-segment bit.
110    pub l: u8,
111    /// The granularity bit: zero for byte, one for 4-KiB granularity.
112    pub g: u8,
113    /// The descriptor bit available to software.
114    pub avl: u8,
115    /// The VMX unusable-segment bit.
116    pub unusable: u8,
117    /// The reserved padding byte.
118    pub padding: u8,
119}
120
121/// Guest descriptor-table state.
122#[repr(C)]
123#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
124pub struct VcpuDescTable {
125    /// The linear base address of the descriptor table.
126    pub base: u64,
127    /// The table size in bytes minus one.
128    pub limit: u16,
129    /// The reserved padding words.
130    pub padding: [u16; 3],
131}
132
133/// Guest MSR state that is not already stored in [`VcpuSregs`].
134#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
135pub struct VcpuMsrs {
136    /// The page attribute table.
137    pub pat: u64,
138    /// The kernel GS base exchanged by `SWAPGS`.
139    pub kernel_gs_base: u64,
140    /// The `SYSCALL` and `SYSRET` segment selectors.
141    pub star: u64,
142    /// The 64-bit `SYSCALL` entry point.
143    pub lstar: u64,
144    /// The compatibility-mode `SYSCALL` entry point.
145    pub cstar: u64,
146    /// The flags cleared on `SYSCALL` entry.
147    pub syscall_mask: u64,
148    /// The accumulated TSC adjustment.
149    pub tsc_adjust: u64,
150    /// The auxiliary TSC value returned by `RDTSCP`.
151    pub tsc_aux: u64,
152    /// The `SYSENTER` code-segment selector.
153    pub sysenter_cs: u64,
154    /// The `SYSENTER` stack pointer.
155    pub sysenter_esp: u64,
156    /// The `SYSENTER` instruction pointer.
157    pub sysenter_eip: u64,
158    /// The miscellaneous processor feature controls.
159    pub misc_enable: u64,
160}
ostd/arch/x86/vm/types.rs

ostd/arch/x86/vm/
types.rs
